The block labeled data bus buffer contains the logic to buffer the data bus to / from the microprocessor, and to the internal registers. The block labeled read / write logic controls the reading and the writing of the counter registers. The final block, the control word register, contains the programmed information that is sent to the device from the microprocessor. In effect this register defines how the 8253 logically works.

Each counter in the block diagram has 3 logical lines connected to it. Two of these lines, clock and gate, are inputs. The third, labeled OUT is an output. The function of these lines changes and depends on how the device is initialized or programmed.

All of the operating modes for the counters are selected by writing bytes to the control register. This is the control word format.

Bits D7 and D6 are labeled SC1 and SC0. These bits select the counter to be programmed, it is necessary to define, using the control bits D7 and D6, which counter is being set up.

Once a counter is set up, it will remain that way until it is changed by another control word.

The final bit D0 of the control register determines how the register will count:

The maximum values for the count in each count mode are 10⁴ ( 10,000 decimal ) in BCD, and 2¹⁶ ( 65,536 decimal ) in binary.

The counter will be programmed to an initial value and afterwards counts down at a rate equal to the input clock frequency. When the count is equal to 0, the OUT pin will be a logical 1. The output will stay a logical 1 until the counter is reloaded with a new value or the same value or until a mode word is written to the device.

Once the counter starts counting down, the GATE input can disable the internal counting by setting the GATE to a logical 0 ( see the table above ).

In mode 1, the device can be setup to give an output pulse that is an integer number of clock pulses. The one-shot is triggered on the rising edge of the GATE input. If the trigger occurs during the pulse output, the 8253 will be retriggered again.

The counter that is programmed for mode 2 becomes a "divide by n" counter. The OUT pin of the counter goes to low for one input clock period. The time between the pulses of going low is dependent on the present count in the counter's register. I mean the time of the logical 1 pulse.

For example, suppose to get an output frequency of 1,000 Hz ( Hertz ), the period would be 1 / 1,000 s = 1 ms ( millisecond ) or 1,000 µs ( microseconds ). If an input clock of 1 MHz ( Mega-Hertz ) were applied to the clock input of the counter #0, then the counter #0 would need to be programmed to 1000 µs. This could be done in decimal or in BCD. ( The period of an input clock of 1 MHz is 1 / 1,000,000 = 1 µs. )

The formula is: n=f_i divided by f_out.
f_i = input clock frequency, f_out = output frequency, n = value to be loaded.

My example: f_i = 1 MHz = 1 x 10⁶ Hz, f_out = 1 kHz = 1 x 10³ Hz.

n = 1 x 10⁶ Hz / 1 x 10³ Hz = 1 x 10³ = 1,000. This is the decimal value to be loaded or the hexadecimal value $03E8. The following program example uses the decimal load count.

B000 3E35	LD	A,$35     ; load control word
			          ; for counter 0 mode 2 
B002 3207E0	LD	($E007),A ; into port $E007
                                  ; for BCD count 
B005 2104E0	LD	HL,$E004  ; address to the port
                                  ; of counter 0 
B008 3E00	LD	A,$00
B00A 77		LD	(HL),A	  ; load least significant
                                  ; byte of 1000 first 
B00B 3E10	LD	A,$10 
B00D 77		LD	(HL),A	  ; load most significant
                                  ; byte of 1000 last 
B00E 3E01	LD	A,1 
B010 3208E0	LD	($E008),A ; start counter 0 is only
                                  ; necessary for the MZ-700.
                                  ; Not necessary for
                                  ; counter #1 and #2 
; 
; The counter is now initialized and the output frequency
; will be 1000 Hz if the input frequency is 1 MHz.  

If the count is loaded between output pulses, the present period will not be affected. A new period will occur during the next count sequence.

Mode 3 is similar to the mode 2 except that the output will be high for half the period and low for half. If the count is odd, the output will be high for ( n + 1 ) / 2 and low for ( n - 1 ) / 2 counts.

For example, I'll setup counter #0 for a square wave frequency of 10 kHz ( kilo-Hertz ), assuming the input frequency is 1 MHz.

Please refer to the formula described at mode 2.
1 x 10⁶ / 10 x 10³ = 100. This is the decimal value to be loaded or the hexadecimal value $0064. The following program example uses the binary load count.

B000 3E35	LD	A,$36	  ; load control word
			          ; for counter 0 mode 3
B002 3207E0	LD	($E007),A ; into port $E007
                                  ; for binary count 
B005 2104E0	LD	HL,$E004  ; address to the port
                          ; of counter 0 
B008 3E00	LD	A,$64	  ; equals to
                                  ; 100 microseconds
                                  ; for 10,000 Hz
B00A 77		LD	(HL),A	  ; load least significant
                                  ; byte of $0064 first 
B00B 3E10	LD	A,$00 
B00D 77		LD	(HL),A	  ; load most significant
                                  ; nyte of $0064 last 
B00E 3E01	LD	A,1 
B010 3208E0	LD	($E008),A ; start counter 0 is only
				  ; necessary for the MZ-700.
                  ; Not necessary for counter
                                  ; #1 and #2 
; 
; The counter is now initialized and the output frequency 
; will be 10 kHz if the input frequency is 1 MHz.  

In this mode the programmer can set up the counter to give an output timeout starting when the register is loaded. On the terminal count, when the counter equals to 0, the output will go to a logical 0 for one clock period and then returns to a logical 1. First the mode is set, the output will be a logical 1.

In this mode the rising edge of the trigger input will start the counting of the counter. The output goes low for one clock at the terminal count. The counter is retriggerable, thus meaning that if the trigger input is taken low and then high during a count sequence, the sequence will start over.

When the external trigger input goes to a logical 1, the timer will start to time out. If the external trigger occurs again, prior to the time completing a full timeout, the timer will retrigger.